Computer - Design Verification & Test of Digital VLSI Circuits

Mod-01 Lec-01 Introduction to Digital VLSI Design Flow
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This introductory module sets the foundation for understanding the entire digital VLSI design flow. It elaborates on the key phases involved in VLSI design, emphasizing the importance of integration among design, verification, and testing. Students will learn about the challenges faced during the design process and how they interlink with verification and testing phases, providing a holistic perspective necessary for designing robust digital circuits.
Mod-01 Lec-02 High Level Design Representation
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers high-level design representation techniques essential for digital VLSI design. Students will explore various abstraction levels and how they facilitate the design process. Key topics include:

Data flow representations

Control flow representations

Finite state machines

By understanding these representations, students can effectively communicate design intent and improve the synthesis process.
Mod-01 Lec-03 Transformations for High Level Synthesis
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module focuses on transformations used in high-level synthesis (HLS). Students will learn about the various techniques employed to optimize designs through transformations such as:

Loop unrolling

Function inlining

Resource sharing

Understanding these transformations is crucial for generating efficient hardware implementations.
Mod-02 Lec-01 Introduction to HLS: Scheduling, Allocation and Binding Problem
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces the core concepts of high-level synthesis, focusing on key problems such as scheduling, allocation, and binding. Students will learn how to:

Determine the order of operations (scheduling)

Allocate resources effectively (allocation)

Assign operations to resources (binding)

These concepts are critical in optimizing the design for performance and resource utilization.
Mod-02 Lec-02 Scheduling Algorithms-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module delves into the first set of scheduling algorithms used in high-level synthesis. Students will learn about various algorithms, their complexity, and their applications in scheduling tasks effectively to meet design requirements.
Mod-02 Lec-03 Scheduling Algorithms-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the discussion on scheduling algorithms, presenting advanced techniques for optimizing scheduling in high-level synthesis. Students will analyze trade-offs between different approaches and their impact on overall design performance.
Mod-02 Lec-04 Binding and Allocation Algorithms
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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In this module, students will discover binding and allocation algorithms crucial for resource management in high-level synthesis. Topics include:

Resource binding techniques

Allocation strategies

Combining binding and allocation processes

Understanding these algorithms helps ensure efficient resource usage within digital designs.
Mod-03 Lec-01 Two level Boolean Logic Synthesis-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces two-level Boolean logic synthesis, where students will explore methods for reducing and optimizing Boolean functions. Key concepts include:

Minimization techniques

Implementation strategies

Comparative analysis of synthesis methods

By mastering these techniques, students will enhance their ability to design efficient digital circuits.
Mod-03 Lec-02 Two level Boolean Logic Synthesis-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the exploration of two-level Boolean logic synthesis, providing deeper insights into advanced minimization techniques and their applications. Students will engage with practical examples to solidify their understanding of these concepts.
Mod-03 Lec-03 Two level Boolean Logic Synthesis-3
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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In this module, students will examine further aspects of two-level Boolean logic synthesis. The focus will be on different algorithms for synthesis and their comparative effectiveness in design.
Mod-03 Lec-04 Heuristic Minimization of Two-Level Circuits
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module focuses on heuristic minimization techniques for two-level circuits. Students will learn about methods to simplify circuits effectively while maintaining functionality. Key topics include:

Heuristic approaches

Optimization methods

Practical applications in circuit design

Understanding these techniques is essential for creating efficient and reliable digital systems.
Mod-03 Lec-05 Finite State Machine Synthesis
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers finite state machine (FSM) synthesis, where students will learn how to design and implement FSMs effectively. Topics include:

FSM modeling techniques

Reduction methods for FSMs

Implementation strategies

Mastering FSM synthesis is crucial for developing control logic within digital systems.
Mod-03 Lec-06 Multilevel Implementation
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces multilevel implementation techniques for digital circuits. Students will explore the advantages of multilevel designs and how they can optimize circuit performance through effective resource utilization.
Mod-04 Lec-01 Introduction to formal methods for design verification
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module provides an introduction to formal methods for design verification. Students will learn foundational concepts and the significance of formal verification in ensuring design correctness, covering topics such as:

Formal specification

Model checking

The role of formal methods in VLSI design

Understanding these methods is essential for building reliable digital systems.
Mod-04 Lec-02 Temporal Logic: Introduction and Basic Operators
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module explores temporal logic, introducing students to its basic operators and their applications in design verification. Key concepts include:

Understanding temporal properties

Applications of temporal logic in verification

Comparison with other verification methods

Mastering temporal logic is vital for effective design verification in digital systems.
Mod-04 Lec-03 Syntax and Semantics of CTL
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers the syntax and semantics of Computation Tree Logic (CTL), providing students with the foundational knowledge required for using CTL in design verification. Topics include:

Basic syntax rules

Semantics interpretation

CTL applications in verification

Understanding CTL is critical for developing robust verification strategies.
Mod-04 Lec-04 Syntax and Semantics of CTL -- Continued
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the discussion on the syntax and semantics of CTL, providing deeper insights into its applications. Students will explore advanced concepts and how they enhance design verification efforts.
Mod-04 Lec-05 Equivalence between CTL Formulas
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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In this module, students will learn about equivalence between CTL formulas, focusing on techniques to compare and analyze different CTL expressions. Understanding equivalence is crucial for ensuring the correctness of verification processes.
Mod-05 Lec-01 Introduction to Model Checking
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module provides an introduction to model checking, where students will explore its principles and applications in verifying digital designs. Key topics include:

Model checking process

Types of model checking

Benefits of model checking in design verification

Understanding model checking is essential for ensuring design correctness.
Mod-05 Lec-02 Model Checking Algorithms I
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module discusses various model checking algorithms, focusing on their design and implementation. Students will analyze the advantages and challenges associated with different algorithms, enhancing their understanding of model checking effectiveness.
Mod-05 Lec-03 Model Checking Algorithms II
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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In this module, students will continue their exploration of model checking algorithms, diving into advanced techniques and methodologies that improve verification efficiency. They will engage with case studies highlighting the application of these algorithms.
Mod-05 Lec-04 Model Checking with Fairness
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module examines model checking with fairness, where students will explore the concepts of fairness in verification processes. Key topics include:

Understanding fairness in models

Incorporating fairness constraints

Applications of fairness in digital design verification

Mastering these concepts is essential for ensuring robust verification methodologies.
Mod-06 Lec-01 Binary Decision Diagram: Introduction and construction
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces Binary Decision Diagrams (BDDs), focusing on their construction and applications in digital design. Students will learn about the advantages of using BDDs for representing Boolean functions and their role in verification.
Mod-06 Lec-02 Ordered Binary Decision Diagram
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module delves into Ordered Binary Decision Diagrams (OBDDs), exploring their efficiency in representing Boolean functions. Students will learn about the ordering strategies and their impact on the performance of BDDs in verification tasks.
Mod-06 Lec-03 Operation on Ordered Binary Decision Diagram
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module discusses operations on Ordered Binary Decision Diagrams (OBDDs), where students will learn about various operations such as conjunction, disjunction, and negation. Understanding these operations is crucial for effective manipulation and application of BDDs in verification.
Mod-06 Lec-04 Ordered Binary Decision Diagram for State Transition Systems
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module explores the use of Ordered Binary Decision Diagrams (OBDDs) for modeling state transition systems. Students will learn how to represent state transitions efficiently, enhancing their ability to analyze and verify complex systems.
Mod-06 Lec-05 Symbolic Model Checking
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces symbolic model checking, where students will learn about symbolic representations in model checking and their advantages over traditional methods. Key topics include:

Symbolic representations

Algorithmic approaches

Case studies demonstrating the effectiveness of symbolic model checking

Understanding these concepts is vital for advancing verification techniques.
Mod-07 Lec-01 Introduction to Digital VLSI Testing
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers the introduction to digital VLSI testing, focusing on fundamental concepts and methodologies necessary for testing digital circuits. Key topics include:

Testing importance and objectives

Testing methodologies and techniques

Overview of testing tools and frameworks

Understanding testing is essential for ensuring robust and reliable digital designs.
Mod-07 Lec-02 Functional and Structural Testing
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module explores functional and structural testing in digital circuits. Students will learn about the differences between these testing approaches, their applications, and the benefits they provide in ensuring design reliability.
Mod-07 Lec-03 Fault Equivalence
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers fault equivalence, discussing how to determine when two faults can be treated as equivalent in testing scenarios. Students will learn about methodologies for analyzing fault behavior and implications for testing efficiency.
Mod-08 Lec-01 Fault Simulation-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces fault simulation, focusing on techniques to simulate faults in digital circuits and evaluate their impact. Topics include:

Fault models

Simulation methodologies

Analysis of simulation results

Understanding fault simulation is crucial for developing effective testing strategies.
Mod-08 Lec-02 Fault Simulation-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the exploration of fault simulation, providing deeper insights into advanced techniques and methodologies that enhance simulation accuracy. Students will engage with practical examples to solidify their understanding of these concepts.
Mod-08 Lec-03 Fault Simulation-3
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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In this module, students will examine additional fault simulation techniques, focusing on various algorithms that optimize simulation processes. Key topics include:

Comparison of algorithms

Application scenarios

Impact on testing efficiency

Understanding these techniques is essential for developing efficient fault simulation methodologies.
Mod-08 Lec-04 Testability Measures (SCOAP)
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces testability measures, specifically the SCOAP (Structural Controllability and Observability Analysis for Programmable logic). Students will learn about:

Testability metrics

Applying SCOAP in design

Impact on testing strategies

Understanding testability measures is vital for improving the design of testable circuits.
Mod-09 Lec-01 Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module provides an introduction to Automatic Test Pattern Generation (ATPG) and ATPG algebras. Students will learn about the significance of ATPG in digital circuit testing, including:

ATPG methodologies

Application scenarios

Benefits of using ATPG

Mastering ATPG is essential for developing efficient testing strategies.
Mod-09 Lec-02 D-Algorithm-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module focuses on the D-algorithm, a significant approach in ATPG. Students will learn about the principles of the D-algorithm, its application in generating test patterns, and its advantages in testing digital circuits.
Mod-09 Lec-03 D-Algorithm-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the exploration of the D-algorithm, presenting advanced techniques and methodologies that enhance its effectiveness in test pattern generation. Students will engage with practical examples to solidify their understanding.
Mod-10 Lec-01 ATPG for Synchronous Sequential Circuits
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces ATPG for synchronous sequential circuits. Students will learn specific techniques and methodologies for testing sequential circuits, covering:

Test generation strategies

Challenges in testing sequential circuits

Implementation examples

Understanding these concepts is vital for developing robust testing methodologies.
Mod-10 Lec-02 Scan Chain based Sequential Circuit Testing-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module covers scan chain-based sequential circuit testing, introducing students to techniques for implementing scan chains effectively. Key topics include:

Scan chain architecture

Test pattern generation for scan chains

Advantages of using scan chains in testing

Understanding scan chain testing is essential for ensuring the reliability of sequential circuits.
Mod-10 Lec-03 Scan Chain based Sequential Circuit Testing-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the exploration of scan chain-based testing, focusing on advanced techniques and practical implementation strategies. Students will engage with real-world examples to enhance their understanding of scan chain testing methodologies.
Mod-11 Lec-01 Built in Self Test-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module introduces Built-In Self Test (BIST) methodologies, focusing on their significance in digital circuit testing. Key topics include:

BIST architecture

Test pattern generation in BIST

Advantages of BIST in improving test efficiency

Mastering BIST concepts is essential for enhancing testing capabilities in digital designs.
Mod-11 Lec-02 Built in Self Test-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the BIST discussion, exploring advanced techniques and methodologies for implementing BIST in digital designs. Students will analyze case studies to better understand the practical applications of BIST strategies.
Mod-11 Lec-03 Memory Testing-1
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module focuses on memory testing methodologies, discussing the importance of testing memory components in digital systems. Key topics include:

Memory fault models

Testing strategies for memory components

Challenges and solutions in memory testing

Understanding memory testing is crucial for ensuring the reliability of digital systems.
Mod-11 Lec-04 Memory Testing-2
Dr. Santosh Biswas, Prof. Jatindra Kumar Deka

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This module continues the exploration of memory testing, providing deeper insights into advanced techniques and methodologies for improving memory testing effectiveness. Students will engage with practical examples to solidify their understanding of these advanced concepts.

Course

Computer - Design Verification & Test of Digital VLSI Circuits

Course Lectures